Coverage for MC6809/components/MC6809data/MC6809_op_docs.py: 100%

1#!/usr/bin/env python 

2# flake8: noqa 

3 

4""" 

5 6809 instruction set data 

6 ~~~~~~~~~~~~~~~~~~~~~~~~~ 

7 

8 merged data from: 

9 * http://www.maddes.net/m6809pm/sections.htm#sec4_4 

10 * http://www.burgins.com/m6809.html 

11 * http://www.maddes.net/m6809pm/appendix_a.htm#appA 

12 

13 Note: 

14 * read_from_memory: it's "excluded" the address modes routines. 

15 So if the address mode will fetch the memory to get the 

16 effective address, but the content of the memory is not needed in 

17 the instruction them self, the read_from_memory must be set to False. 

18 

19 Generated data is online here: 

20 https://docs.google.com/spreadsheet/ccc?key=0Alhtym6D6yKjdFBtNmF0UVR5OW05S3psaURnUTNtSFE 

21 

22 :copyleft: 2013-2014 by Jens Diemer 

23 :license: GNU GPL v3 or above, see LICENSE for more details. 

24""" 

25 

26OP_DOC = {'ABX': {'condition code': 'Not affected.', 

27 'description': 'Add the 8-bit unsigned value in accumulator B into index register X.', 

28 'instr_desc': 'Add B accumulator to X (unsigned)', 

29 'mnemonic': {'ABX': {'HNZVC': '-----', 

30 'desc': 'X = B+X (Unsigned)'}}, 

31 'operation': "IX' = IX + ACCB", 

32 'source form': 'ABX'}, 

33 'ADC': {'condition code': ( 

34 'H - Set if a half-carry is generated; cleared otherwise.\n' 

35 'N - Set if the result is negative; cleared otherwise.\n' 

36 'Z - Set if the result is zero; cleared otherwise.\n' 

37 'V - Set if an overflow is generated; cleared otherwise.\n' 

38 'C - Set if a carry is generated; cleared otherwise.' 

39 ), 

40 'description': 'Adds the contents of the C (carry) bit and the memory byte into an 8-bit accumulator.', 

41 'instr_desc': 'Add memory to accumulator with carry', 

42 'mnemonic': {'ADCA': {'HNZVC': 'aaaaa', 

43 'desc': 'A = A+M+C'}, 

44 'ADCB': {'HNZVC': 'aaaaa', 

45 'desc': 'B = B+M+C'}}, 

46 'operation': "R' = R + M + C", 

47 'source form': 'ADCA P; ADCB P'}, 

48 'ADD': {'condition code': ( 

49 'H - Set if a half-carry is generated; cleared otherwise.\n' 

50 'N - Set if the result is negative; cleared otherwise.\n' 

51 'Z - Set if the result is zero; cleared otherwise.\n' 

52 'V - Set if an overflow is generated; cleared otherwise.\n' 

53 'C - Set if a carry is generated; cleared otherwise.' 

54 ), 

55 'description': 'Adds the memory byte into an 8-bit accumulator.', 

56 'instr_desc': 'Add memory to accumulator', 

57 'mnemonic': {'ADDA': {'HNZVC': 'aaaaa', 

58 'desc': 'A = A+M'}, 

59 'ADDB': {'HNZVC': 'aaaaa', 

60 'desc': 'B = B+M'}, 

61 'ADDD': {'HNZVC': '-aaaa', 

62 'desc': 'D = D+M:M+1'}}, 

63 'operation': "R' = R + M", 

64 'source form': 'ADDA P; ADDB P'}, 

65 'AND': {'condition code': ( 

66 'H - Not affected.\n' 

67 'N - Set if the result is negative; cleared otherwise.\n' 

68 'Z - Set if the result is zero; cleared otherwise.\n' 

69 'V - Always cleared.\n' 

70 'C - Not affected.' 

71 ), 

72 'description': 'Performs the logical AND operation between the contents of an accumulator and the contents of memory location M and the result is stored in the accumulator.', 

73 'instr_desc': 'AND memory with accumulator', 

74 'mnemonic': {'ANDA': {'HNZVC': '-aa0-', 

75 'desc': 'A = A && M'}, 

76 'ANDB': {'HNZVC': '-aa0-', 

77 'desc': 'B = B && M'}, 

78 'ANDCC': {'HNZVC': 'ddddd', 

79 'desc': 'C = CC && IMM'}}, 

80 'operation': "R' = R AND M", 

81 'source form': 'ANDA P; ANDB P'}, 

82 'ASR': {'condition code': ( 

83 'H - Undefined.\n' 

84 'N - Set if the result is negative; cleared otherwise.\n' 

85 'Z - Set if the result is zero; cleared otherwise.\n' 

86 'V - Not affected.\n' 

87 'C - Loaded with bit zero of the original operand.' 

88 ), 

89 'description': 'Shifts all bits of the operand one place to the right. Bit seven is held constant. Bit zero is shifted into the C (carry) bit.', 

90 'instr_desc': 'Arithmetic shift of accumulator or memory right', 

91 'mnemonic': {'ASR': {'HNZVC': 'uaa-s', 

92 'desc': 'M = Arithmetic shift M right'}, 

93 'ASRA': {'HNZVC': 'uaa-s', 

94 'desc': 'A = Arithmetic shift A right'}, 

95 'ASRB': {'HNZVC': 'uaa-s', 

96 'desc': 'B = Arithmetic shift B right'}}, 

97 'operation': ( 

98 'b7 -> -> C\n' 

99 'b7 -> b0' 

100 ), 

101 'source form': 'ASR Q; ASRA; ASRB'}, 

102 'BEQ': {'condition code': 'Not affected.', 

103 'description': ( 

104 'Tests the state of the Z (zero) bit and causes a branch if it is set.\n' 

105 'When used after a subtract or compare operation, this instruction will branch if the compared values, signed or unsigned, were exactly the same.' 

106 ), 

107 'instr_desc': 'Branch if equal', 

108 'mnemonic': {'BEQ': {'HNZVC': '-----', 

109 'desc': None}, 

110 'LBEQ': {'HNZVC': '-----', 

111 'desc': None}}, 

112 'operation': "TEMP = MI IFF Z = 1 then PC' = PC + TEMP", 

113 'source form': 'BEQ dd; LBEQ DDDD'}, 

114 'BGE': {'condition code': 'Not affected.', 

115 'description': ( 

116 'Causes a branch if the N (negative) bit and the V (overflow) bit are either both set or both clear.\n' 

117 'That is, branch if the sign of a valid twos complement result is, or would be, positive.\n' 

118 'When used after a subtract or compare operation on twos complement values, this instruction will branch if the register was greater than or equal to the memory operand.' 

119 ), 

120 'instr_desc': 'Branch if greater than or equal (signed)', 

121 'mnemonic': {'BGE': {'HNZVC': '-----', 

122 'desc': None}, 

123 'LBGE': {'HNZVC': '-----', 

124 'desc': None}}, 

125 'operation': "TEMP = MI IFF [N XOR V] = 0 then PC' = PC + TEMP", 

126 'source form': 'BGE dd; LBGE DDDD'}, 

127 'BGT': {'condition code': 'Not affected.', 

128 'description': ( 

129 'Causes a branch if the N (negative) bit and V (overflow) bit are either both set or both clear and the Z (zero) bit is clear.\n' 

130 'In other words, branch if the sign of a valid twos complement result is, or would be, positive and not zero.\n' 

131 'When used after a subtract or compare operation on twos complement values, this instruction will branch if the register was greater than the memory operand.' 

132 ), 

133 'instr_desc': 'Branch if greater (signed)', 

134 'mnemonic': {'BGT': {'HNZVC': '-----', 

135 'desc': None}, 

136 'LBGT': {'HNZVC': '-----', 

137 'desc': None}}, 

138 'operation': "TEMP = MI IFF Z AND [N XOR V] = 0 then PC' = PC + TEMP", 

139 'source form': 'BGT dd; LBGT DDDD'}, 

140 'BHI': {'comment': 'Generally not useful after INC/DEC, LD/TST, and TST/CLR/COM instructions.', 

141 'condition code': 'Not affected.', 

142 'description': ( 

143 'Causes a branch if the previous operation caused neither a carry nor a zero result.\n' 

144 'When used after a subtract or compare operation on unsigned binary values, this instruction will branch if the register was higher than the memory operand.' 

145 ), 

146 'instr_desc': 'Branch if higher (unsigned)', 

147 'mnemonic': {'BHI': {'HNZVC': '-----', 

148 'desc': None}, 

149 'LBHI': {'HNZVC': '-----', 

150 'desc': None}}, 

151 'operation': "TEMP = MI IFF [ C OR Z ] = 0 then PC' = PC + TEMP", 

152 'source form': 'BHI dd; LBHI DDDD'}, 

153 'BHS': {'comment': ( 

154 'This is a duplicate assembly-language mnemonic for the single machine instruction BCC.\n' 

155 'Generally not useful after INC/DEC, LD/ST, and TST/CLR/COM instructions.' 

156 ), 

157 'condition code': 'Not affected.', 

158 'description': ( 

159 'Tests the state of the C (carry) bit and causes a branch if it is clear.\n' 

160 'When used after a subtract or compare on unsigned binary values, this instruction will branch if the register was higher than or the same as the memory operand.' 

161 ), 

162 'instr_desc': 'Branch if higher or same (unsigned)', 

163 'mnemonic': {'BCC': {'HNZVC': '-----', 

164 'desc': None}, 

165 'LBCC': {'HNZVC': '-----', 

166 'desc': None}}, 

167 'operation': "TEMP = MI IFF C = 0 then PC' = PC + MI", 

168 'source form': 'BHS dd; LBHS DDDD'}, 

169 'BIT': {'condition code': ( 

170 'H - Not affected.\n' 

171 'N - Set if the result is negative; cleared otherwise.\n' 

172 'Z - Set if the result is zero; cleared otherwise.\n' 

173 'V - Always cleared.\n' 

174 'C - Not affected.' 

175 ), 

176 'description': ( 

177 'Performs the logical AND of the contents of accumulator A or B and the contents of memory location M and modifies the condition codes accordingly.\n' 

178 'The contents of accumulator A or B and memory location M are not affected.' 

179 ), 

180 'instr_desc': 'Bit test memory with accumulator', 

181 'mnemonic': {'BITA': {'HNZVC': '-aa0-', 

182 'desc': 'Bit Test A (M&&A)'}, 

183 'BITB': {'HNZVC': '-aa0-', 

184 'desc': 'Bit Test B (M&&B)'}}, 

185 'operation': 'TEMP = R AND M', 

186 'source form': 'BITA P; BITB P'}, 

187 'BLE': {'condition code': 'Not affected.', 

188 'description': ( 

189 'Causes a branch if the exclusive OR of the N (negative) and V (overflow) bits is 1 or if the Z (zero) bit is set.\n' 

190 'That is, branch if the sign of a valid twos complement result is, or would be, negative.\n' 

191 'When used after a subtract or compare operation on twos complement values, this instruction will branch if the register was less than or equal to the memory operand.' 

192 ), 

193 'instr_desc': 'Branch if less than or equal (signed)', 

194 'mnemonic': {'BLE': {'HNZVC': '-----', 

195 'desc': None}, 

196 'LBLE': {'HNZVC': '-----', 

197 'desc': None}}, 

198 'operation': "TEMP = MI IFF Z OR [ N XOR V ] = 1 then PC' = PC + TEMP", 

199 'source form': 'BLE dd; LBLE DDDD'}, 

200 'BLO': {'comment': ( 

201 'This is a duplicate assembly-language mnemonic for the single machine instruction BCS.\n' 

202 'Generally not useful after INC/DEC, LD/ST, and TST/CLR/COM instructions.' 

203 ), 

204 'condition code': 'Not affected.', 

205 'description': ( 

206 'Tests the state of the C (carry) bit and causes a branch if it is set.\n' 

207 'When used after a subtract or compare on unsigned binary values, this instruction will branch if the register was lower than the memory operand.' 

208 ), 

209 'instr_desc': 'Branch if lower (unsigned)', 

210 'mnemonic': {'BLO': {'HNZVC': '-----', 

211 'desc': None}, 

212 'LBCS': {'HNZVC': '-----', 

213 'desc': None}}, 

214 'operation': "TEMP = MI IFF C = 1 then PC' = PC + TEMP", 

215 'source form': 'BLO dd; LBLO DDDD'}, 

216 'BLS': {'comment': 'Generally not useful after INC/DEC, LD/ST, and TST/CLR/COM instructions.', 

217 'condition code': 'Not affected.', 

218 'description': ( 

219 'Causes a branch if the previous operation caused either a carry or a zero result.\n' 

220 'When used after a subtract or compare operation on unsigned binary values, this instruction will branch if the register was lower than or the same as the memory operand.' 

221 ), 

222 'instr_desc': 'Branch if lower or same (unsigned)', 

223 'mnemonic': {'BLS': {'HNZVC': '-----', 

224 'desc': None}, 

225 'LBLS': {'HNZVC': '-----', 

226 'desc': None}}, 

227 'operation': "TEMP = MI IFF (C OR Z) = 1 then PC' = PC + TEMP", 

228 'source form': 'BLS dd; LBLS DDDD'}, 

229 'BLT': {'condition code': 'Not affected.', 

230 'description': ( 

231 'Causes a branch if either, but not both, of the N (negative) or V (overflow) bits is set.\n' 

232 'That is, branch if the sign of a valid twos complement result is, or would be, negative.\n' 

233 'When used after a subtract or compare operation on twos complement binary values, this instruction will branch if the register was less than the memory operand.' 

234 ), 

235 'instr_desc': 'Branch if less than (signed)', 

236 'mnemonic': {'BLT': {'HNZVC': '-----', 

237 'desc': None}, 

238 'LBLT': {'HNZVC': '-----', 

239 'desc': None}}, 

240 'operation': "TEMP = MI IFF [ N XOR V ] = 1 then PC' = PC + TEMP", 

241 'source form': 'BLT dd; LBLT DDDD'}, 

242 'BMI': {'comment': ( 

243 'When used after an operation on signed binary values, this instruction will branch if the result is minus.\n' 

244 'It is generally preferred to use the LBLT instruction after signed operations.' 

245 ), 

246 'condition code': 'Not affected.', 

247 'description': ( 

248 'Tests the state of the N (negative) bit and causes a branch if set.\n' 

249 'That is, branch if the sign of the twos complement result is negative.' 

250 ), 

251 'instr_desc': 'Branch if minus', 

252 'mnemonic': {'BMI': {'HNZVC': '-----', 

253 'desc': None}, 

254 'LBMI': {'HNZVC': '-----', 

255 'desc': None}}, 

256 'operation': "TEMP = MI IFF N = 1 then PC' = PC + TEMP", 

257 'source form': 'BMI dd; LBMI DDDD'}, 

258 'BNE': {'condition code': 'Not affected.', 

259 'description': ( 

260 'Tests the state of the Z (zero) bit and causes a branch if it is clear.\n' 

261 'When used after a subtract or compare operation on any binary values, this instruction will branch if the register is, or would be, not equal to the memory operand.' 

262 ), 

263 'instr_desc': 'Branch if not equal', 

264 'mnemonic': {'BNE': {'HNZVC': '-----', 

265 'desc': None}, 

266 'LBNE': {'HNZVC': '-----', 

267 'desc': None}}, 

268 'operation': "TEMP = MI IFF Z = 0 then PC' = PC + TEMP", 

269 'source form': 'BNE dd; LBNE DDDD'}, 

270 'BPL': {'comment': ( 

271 'When used after an operation on signed binary values, this instruction will branch if the result (possibly invalid) is positive.\n' 

272 'It is generally preferred to use the BGE instruction after signed operations.' 

273 ), 

274 'condition code': 'Not affected.', 

275 'description': ( 

276 'Tests the state of the N (negative) bit and causes a branch if it is clear.\n' 

277 'That is, branch if the sign of the twos complement result is positive.' 

278 ), 

279 'instr_desc': 'Branch if plus', 

280 'mnemonic': {'BPL': {'HNZVC': '-----', 

281 'desc': None}, 

282 'LBPL': {'HNZVC': '-----', 

283 'desc': None}}, 

284 'operation': "TEMP = MI IFF N = 0 then PC' = PC + TEMP", 

285 'source form': 'BPL dd; LBPL DDDD'}, 

286 'BRA': {'condition code': 'Not affected.', 

287 'description': 'Causes an unconditional branch.', 

288 'instr_desc': 'Branch always', 

289 'mnemonic': {'BRA': {'HNZVC': '-----', 

290 'desc': None}, 

291 'LBRA': {'HNZVC': '-----', 

292 'desc': None}}, 

293 'operation': "TEMP = MI PC' = PC + TEMP", 

294 'source form': 'BRA dd; LBRA DDDD'}, 

295 'BRN': {'condition code': 'Not affected.', 

296 'description': ( 

297 'Does not cause a branch.\n' 

298 'This instruction is essentially a no operation, but has a bit pattern logically related to branch always.' 

299 ), 

300 'instr_desc': 'Branch never', 

301 'mnemonic': {'BRN': {'HNZVC': '-----', 

302 'desc': None}, 

303 'LBRN': {'HNZVC': '-----', 

304 'desc': None}}, 

305 'operation': 'TEMP = MI', 

306 'source form': 'BRN dd; LBRN DDDD'}, 

307 'BSR': {'comment': 'A return from subroutine (RTS) instruction is used to reverse this process and must be the last instruction executed in a subroutine.', 

308 'condition code': 'Not affected.', 

309 'description': ( 

310 'The program counter is pushed onto the stack.\n' 

311 'The program counter is then loaded with the sum of the program counter and the offset.' 

312 ), 

313 'instr_desc': 'Branch to subroutine', 

314 'mnemonic': {'BSR': {'HNZVC': '-----', 

315 'desc': None}, 

316 'LBSR': {'HNZVC': '-----', 

317 'desc': None}}, 

318 'operation': "TEMP = MI SP' = SP-1, (SP) = PCL SP' = SP-1, (SP) = PCH PC' = PC + TEMP", 

319 'source form': 'BSR dd; LBSR DDDD'}, 

320 'BVC': {'condition code': 'Not affected.', 

321 'description': ( 

322 'Tests the state of the V (overflow) bit and causes a branch if it is clear.\n' 

323 'That is, branch if the twos complement result was valid.\n' 

324 'When used after an operation on twos complement binary values, this instruction will branch if there was no overflow.' 

325 ), 

326 'instr_desc': 'Branch if valid twos complement result', 

327 'mnemonic': {'BVC': {'HNZVC': '-----', 

328 'desc': None}, 

329 'LBVC': {'HNZVC': '-----', 

330 'desc': None}}, 

331 'operation': "TEMP = MI IFF V = 0 then PC' = PC + TEMP", 

332 'source form': 'BVC dd; LBVC DDDD'}, 

333 'BVS': {'condition code': 'Not affected.', 

334 'description': ( 

335 'Tests the state of the V (overflow) bit and causes a branch if it is set.\n' 

336 'That is, branch if the twos complement result was invalid.\n' 

337 'When used after an operation on twos complement binary values, this instruction will branch if there was an overflow.' 

338 ), 

339 'instr_desc': 'Branch if invalid twos complement result', 

340 'mnemonic': {'BVS': {'HNZVC': '-----', 

341 'desc': None}, 

342 'LBVS': {'HNZVC': '-----', 

343 'desc': None}}, 

344 'operation': "TEMP' = MI IFF V = 1 then PC' = PC + TEMP", 

345 'source form': 'BVS dd; LBVS DDDD'}, 

346 'CLR': {'condition code': ( 

347 'H - Not affected.\n' 

348 'N - Always cleared.\n' 

349 'Z - Always set.\n' 

350 'V - Always cleared.\n' 

351 'C - Always cleared.' 

352 ), 

353 'description': ( 

354 'Accumulator A or B or memory location M is loaded with 00000000 2 .\n' 

355 'Note that the EA is read during this operation.' 

356 ), 

357 'instr_desc': 'Clear accumulator or memory location', 

358 'mnemonic': {'CLR': {'HNZVC': '-0100', 

359 'desc': 'M = 0'}, 

360 'CLRA': {'HNZVC': '-0100', 

361 'desc': 'A = 0'}, 

362 'CLRB': {'HNZVC': '-0100', 

363 'desc': 'B = 0'}}, 

364 'operation': 'TEMP = M M = 00 16', 

365 'source form': 'CLR Q'}, 

366 'CMP': {'condition code': ( 

367 'H - Undefined.\n' 

368 'N - Set if the result is negative; cleared otherwise.\n' 

369 'Z - Set if the result is zero; cleared otherwise.\n' 

370 'V - Set if an overflow is generated; cleared otherwise.\n' 

371 'C - Set if a borrow is generated; cleared otherwise.' 

372 ), 

373 'description': ( 

374 'Compares the contents of memory location to the contents of the specified register and sets the appropriate condition codes.\n' 

375 'Neither memory location M nor the specified register is modified.\n' 

376 'The carry flag represents a borrow and is set to the inverse of the resulting binary carry.' 

377 ), 

378 'instr_desc': 'Compare memory from accumulator', 

379 'mnemonic': {'CMPA': {'HNZVC': 'uaaaa', 

380 'desc': 'Compare M from A'}, 

381 'CMPB': {'HNZVC': 'uaaaa', 

382 'desc': 'Compare M from B'}, 

383 'CMPD': {'HNZVC': '-aaaa', 

384 'desc': 'Compare M:M+1 from D'}, 

385 'CMPS': {'HNZVC': '-aaaa', 

386 'desc': 'Compare M:M+1 from S'}, 

387 'CMPU': {'HNZVC': '-aaaa', 

388 'desc': 'Compare M:M+1 from U'}, 

389 'CMPX': {'HNZVC': '-aaaa', 

390 'desc': 'Compare M:M+1 from X'}, 

391 'CMPY': {'HNZVC': '-aaaa', 

392 'desc': 'Compare M:M+1 from Y'}}, 

393 'operation': 'TEMP = R - M', 

394 'source form': 'CMPA P; CMPB P'}, 

395 'COM': {'condition code': ( 

396 'H - Not affected.\n' 

397 'N - Set if the result is negative; cleared otherwise.\n' 

398 'Z - Set if the result is zero; cleared otherwise.\n' 

399 'V - Always cleared.\n' 

400 'C - Always set.' 

401 ), 

402 'description': ( 

403 'Replaces the contents of memory location M or accumulator A or B with its logical complement.\n' 

404 'When operating on unsigned values, only BEQ and BNE branches can be expected to behave properly following a COM instruction.\n' 

405 'When operating on twos complement values, all signed branches are available.' 

406 ), 

407 'instr_desc': 'Complement accumulator or memory location', 

408 'mnemonic': {'COM': {'HNZVC': '-aa01', 

409 'desc': 'M = complement(M)'}, 

410 'COMA': {'HNZVC': '-aa01', 

411 'desc': 'A = complement(A)'}, 

412 'COMB': {'HNZVC': '-aa01', 

413 'desc': 'B = complement(B)'}}, 

414 'operation': "M' = 0 + M", 

415 'source form': 'COM Q; COMA; COMB'}, 

416 'CWAI': {'comment': 'The following immediate values will have the following results: FF = enable neither EF = enable IRQ BF = enable FIRQ AF = enable both', 

417 'condition code': 'Affected according to the operation.', 

418 'description': ( 

419 'This instruction ANDs an immediate byte with the condition code register which may clear the interrupt mask bits I and F, stacks the entire machine state on the hardware stack and then looks for an interrupt.\n' 

420 'When a non-masked interrupt occurs, no further machine state information need be saved before vectoring to the interrupt handling routine.\n' 

421 'This instruction replaced the MC6800 CLI WAI sequence, but does not place the buses in a high-impedance state.\n' 

422 'A FIRQ (fast interrupt request) may enter its interrupt handler with its entire machine state saved.\n' 

423 'The RTI (return from interrupt) instruction will automatically return the entire machine state after testing the E (entire) bit of the recovered condition code register.' 

424 ), 

425 'instr_desc': 'AND condition code register, then wait for interrupt', 

426 'mnemonic': {'CWAI': {'HNZVC': 'ddddd', 

427 'desc': 'CC = CC ^ IMM; (Wait for Interrupt)'}}, 

428 'operation': "CCR = CCR AND MI (Possibly clear masks) Set E (entire state saved) SP' = SP-1, (SP) = PCL SP' = SP-1, (SP) = PCH SP' = SP-1, (SP) = USL SP' = SP-1, (SP) = USH SP' = SP-1, (SP) = IYL SP' = SP-1, (SP) = IYH SP' = SP-1, (SP) = IXL SP' = SP-1, (SP) = IXH SP' = SP-1, (SP) = DPR SP' = SP-1, (SP) = ACCB SP' = SP-1, (SP) = ACCA SP' = SP-1, (SP) = CCR", 

429 'source form': 'CWAI #$XX E F H I N Z V C'}, 

430 'DAA': {'condition code': ( 

431 'H - Not affected.\n' 

432 'N - Set if the result is negative; cleared otherwise.\n' 

433 'Z - Set if the result is zero; cleared otherwise.\n' 

434 'V - Undefined.\n' 

435 'C - Set if a carry is generated or if the carry bit was set before the operation; cleared otherwise.' 

436 ), 

437 'description': ( 

438 'The sequence of a single-byte add instruction on accumulator A (either ADDA or ADCA) and a following decimal addition adjust instruction results in a BCD addition with an appropriate carry bit.\n' 

439 'Both values to be added must be in proper BCD form (each nibble such that: 0 <= nibble <= 9).\n' 

440 'Multiple-precision addition must add the carry generated by this decimal addition adjust into the next higher digit during the add operation (ADCA) immediately prior to the next decimal addition adjust.' 

441 ), 

442 'instr_desc': 'Decimal adjust A accumulator', 

443 'mnemonic': {'DAA': {'HNZVC': '-aa0a', 

444 'desc': 'Decimal Adjust A'}}, 

445 'operation': 'Decimal Adjust A', 

446 'source form': 'DAA'}, 

447 'DEC': {'condition code': ( 

448 'H - Not affected.\n' 

449 'N - Set if the result is negative; cleared otherwise.\n' 

450 'Z - Set if the result is zero; cleared otherwise.\n' 

451 'V - Set if the original operand was 10000000 2 ; cleared otherwise.\n' 

452 'C - Not affected.' 

453 ), 

454 'description': ( 

455 'Subtract one from the operand.\n' 

456 'The carry bit is not affected, thus allowing this instruction to be used as a loop counter in multiple-precision computations.\n' 

457 'When operating on unsigned values, only BEQ and BNE branches can be expected to behave consistently.\n' 

458 'When operating on twos complement values, all signed branches are available.' 

459 ), 

460 'instr_desc': 'Decrement accumulator or memory location', 

461 'mnemonic': {'DEC': {'HNZVC': '-aaa-', 

462 'desc': 'M = M - 1'}, 

463 'DECA': {'HNZVC': '-aaa-', 

464 'desc': 'A = A - 1'}, 

465 'DECB': {'HNZVC': '-aaa-', 

466 'desc': 'B = B - 1'}}, 

467 'operation': "M' = M - 1", 

468 'source form': 'DEC Q; DECA; DECB'}, 

469 'EOR': {'condition code': ( 

470 'H - Not affected.\n' 

471 'N - Set if the result is negative; cleared otherwise.\n' 

472 'Z - Set if the result is zero; cleared otherwise.\n' 

473 'V - Always cleared.\n' 

474 'C - Not affected.' 

475 ), 

476 'description': 'The contents of memory location M is exclusive ORed into an 8-bit register.', 

477 'instr_desc': 'Exclusive OR memory with accumulator', 

478 'mnemonic': {'EORA': {'HNZVC': '-aa0-', 

479 'desc': 'A = A XOR M'}, 

480 'EORB': {'HNZVC': '-aa0-', 

481 'desc': 'B = M XOR B'}}, 

482 'operation': "R' = R XOR M", 

483 'source form': 'EORA P; EORB P'}, 

484 'EXG': {'condition code': ( 

485 'Not affected (unless one of the registers is the condition code\n' 

486 'register).' 

487 ), 

488 'description': ( 

489 '0000 = A:B 1000 = A\n' 

490 '0001 = X 1001 = B\n' 

491 '0010 = Y 1010 = CCR\n' 

492 '0011 = US 1011 = DPR\n' 

493 '0100 = SP 1100 = Undefined\n' 

494 '0101 = PC 1101 = Undefined\n' 

495 '0110 = Undefined 1110 = Undefined\n' 

496 '0111 = Undefined 1111 = Undefined' 

497 ), 

498 'instr_desc': 'Exchange Rl with R2', 

499 'mnemonic': {'EXG': {'HNZVC': 'ccccc', 

500 'desc': 'exchange R1,R2'}}, 

501 'operation': 'R1 <-> R2', 

502 'source form': 'EXG R1,R2'}, 

503 'INC': {'condition code': ( 

504 'H - Not affected.\n' 

505 'N - Set if the result is negative; cleared otherwise.\n' 

506 'Z - Set if the result is zero; cleared otherwise.\n' 

507 'V - Set if the original operand was 01111111 2 ; cleared otherwise.\n' 

508 'C - Not affected.' 

509 ), 

510 'description': ( 

511 'Adds to the operand.\n' 

512 'The carry bit is not affected, thus allowing this instruction to be used as a loop counter in multiple-precision computations.\n' 

513 'When operating on unsigned values, only the BEQ and BNE branches can be expected to behave consistently.\n' 

514 'When operating on twos complement values, all signed branches are correctly available.' 

515 ), 

516 'instr_desc': 'Increment accumulator or memory location', 

517 'mnemonic': {'INC': {'HNZVC': '-aaa-', 

518 'desc': 'M = M + 1'}, 

519 'INCA': {'HNZVC': '-aaa-', 

520 'desc': 'A = A + 1'}, 

521 'INCB': {'HNZVC': '-aaa-', 

522 'desc': 'B = B + 1'}}, 

523 'operation': "M' = M + 1", 

524 'source form': 'INC Q; INCA; INCB'}, 

525 'JMP': {'condition code': 'Not affected.', 

526 'description': 'Program control is transferred to the effective address.', 

527 'instr_desc': 'Jump', 

528 'mnemonic': {'JMP': {'HNZVC': '-----', 

529 'desc': 'pc = EA'}}, 

530 'operation': "PC' = EA", 

531 'source form': 'JMP EA'}, 

532 'JSR': {'condition code': 'Not affected.', 

533 'description': ( 

534 'Program control is transferred to the effective address after storing the return address on the hardware stack.\n' 

535 'A RTS instruction should be the last executed instruction of the subroutine.' 

536 ), 

537 'instr_desc': 'Jump to subroutine', 

538 'mnemonic': {'JSR': {'HNZVC': '-----', 

539 'desc': 'jump to subroutine'}}, 

540 'operation': "SP' = SP-1, (SP) = PCL SP' = SP-1, (SP) = PCH PC' =EA", 

541 'source form': 'JSR EA'}, 

542 'LD': {'condition code': ( 

543 'H - Not affected.\n' 

544 'N - Set if the loaded data is negative; cleared otherwise.\n' 

545 'Z - Set if the loaded data is zero; cleared otherwise.\n' 

546 'V - Always cleared.\n' 

547 'C - Not affected.' 

548 ), 

549 'description': 'Loads the contents of memory location M into the designated register.', 

550 'instr_desc': 'Load accumulator from memory', 

551 'mnemonic': {'LDA': {'HNZVC': '-aa0-', 

552 'desc': 'A = M'}, 

553 'LDB': {'HNZVC': '-aa0-', 

554 'desc': 'B = M'}, 

555 'LDD': {'HNZVC': '-aa0-', 

556 'desc': 'D = M:M+1'}, 

557 'LDS': {'HNZVC': '-aa0-', 

558 'desc': 'S = M:M+1'}, 

559 'LDU': {'HNZVC': '-aa0-', 

560 'desc': 'U = M:M+1'}, 

561 'LDX': {'HNZVC': '-aa0-', 

562 'desc': 'X = M:M+1'}, 

563 'LDY': {'HNZVC': '-aa0-', 

564 'desc': 'Y = M:M+1'}}, 

565 'operation': "R' = M", 

566 'source form': 'LDA P; LDB P'}, 

567 'LEA': {'comment': ( 

568 'Instruction Operation Comment\n' 

569 'Instruction\n' 

570 '\n' 

571 'Operation\n' 

572 '\n' 

573 'Comment\n' 

574 'LEAX 10,X X+10 -> X Adds 5-bit constant 10 to X\n' 

575 'LEAX 500,X X+500 -> X Adds 16-bit constant 500 to X\n' 

576 'LEAY A,Y Y+A -> Y Adds 8-bit accumulator to Y\n' 

577 'LEAY D,Y Y+D -> Y Adds 16-bit D accumulator to Y\n' 

578 'LEAU -10,U U-10 -> U Subtracts 10 from U\n' 

579 'LEAS -10,S S-10 -> S Used to reserve area on stack\n' 

580 "LEAS 10,S S+10 -> S Used to 'clean up' stack\n" 

581 'LEAX 5,S S+5 -> X Transfers as well as adds' 

582 ), 

583 'condition code': ( 

584 'H - Not affected.\n' 

585 'N - Not affected.\n' 

586 'Z - LEAX, LEAY: Set if the result is zero; cleared otherwise. LEAS, LEAU: Not affected.\n' 

587 'V - Not affected.\n' 

588 'C - Not affected.' 

589 ), 

590 'description': 'Calculates the effective address from the indexed addressing mode and places the address in an indexable register. LEAX and LEAY affect the Z (zero) bit to allow use of these registers as counters and for MC6800 INX/DEX compatibility. LEAU and LEAS do not affect the Z bit to allow cleaning up the stack while returning the Z bit as a parameter to a calling routine, and also for MC6800 INS/DES compatibility.', 

591 'instr_desc': 'Load effective address into stack pointer', 

592 'mnemonic': {'LEAS': {'HNZVC': '-----', 

593 'desc': 'S = EA'}, 

594 'LEAU': {'HNZVC': '-----', 

595 'desc': 'U = EA'}, 

596 'LEAX': {'HNZVC': '--a--', 

597 'desc': 'X = EA'}, 

598 'LEAY': {'HNZVC': '--a--', 

599 'desc': 'Y = EA'}}, 

600 'operation': "R' = EA", 

601 'source form': 'LEAX, LEAY, LEAS, LEAU'}, 

602 'LSL': {'comment': 'This is a duplicate assembly-language mnemonic for the single machine instruction ASL.', 

603 'condition code': ( 

604 'H - Undefined.\n' 

605 'N - Set if the result is negative; cleared otherwise.\n' 

606 'Z - Set if the result is zero; cleared otherwise.\n' 

607 'V - Loaded with the result of the exclusive OR of bits six and seven of the original operand.\n' 

608 'C - Loaded with bit seven of the original operand.' 

609 ), 

610 'description': ( 

611 'Shifts all bits of accumulator A or B or memory location M one place to the left.\n' 

612 'Bit zero is loaded with a zero.\n' 

613 'Bit seven of accumulator A or B or memory location M is shifted into the C (carry) bit.' 

614 ), 

615 'instr_desc': 'Logical shift left accumulator or memory location', 

616 'mnemonic': {'LSL': {'HNZVC': 'naaas', 

617 'desc': 'M = Logical shift M left'}, 

618 'LSLA': {'HNZVC': 'naaas', 

619 'desc': 'A = Logical shift A left'}, 

620 'LSLB': {'HNZVC': 'naaas', 

621 'desc': 'B = Logical shift B left'}}, 

622 'operation': ( 

623 'C = = 0\n' 

624 'b7 = b0' 

625 ), 

626 'source form': 'LSL Q; LSLA; LSLB'}, 

627 'LSR': {'condition code': ( 

628 'H - Not affected.\n' 

629 'N - Always cleared.\n' 

630 'Z - Set if the result is zero; cleared otherwise.\n' 

631 'V - Not affected.\n' 

632 'C - Loaded with bit zero of the original operand.' 

633 ), 

634 'description': ( 

635 'Performs a logical shift right on the operand.\n' 

636 'Shifts a zero into bit seven and bit zero into the C (carry) bit.' 

637 ), 

638 'instr_desc': 'Logical shift right accumulator or memory location', 

639 'mnemonic': {'LSR': {'HNZVC': '-0a-s', 

640 'desc': 'M = Logical shift M right'}, 

641 'LSRA': {'HNZVC': '-0a-s', 

642 'desc': 'A = Logical shift A right'}, 

643 'LSRB': {'HNZVC': '-0a-s', 

644 'desc': 'B = Logical shift B right'}}, 

645 'operation': ( 

646 '0 -> -> C\n' 

647 'b7 -> b0' 

648 ), 

649 'source form': 'LSR Q; LSRA; LSRB'}, 

650 'MUL': {'comment': 'The C (carry) bit allows rounding the most-significant byte through the sequence: MUL, ADCA #0.', 

651 'condition code': ( 

652 'H - Not affected.\n' 

653 'N - Not affected.\n' 

654 'Z - Set if the result is zero; cleared otherwise.\n' 

655 'V - Not affected.\n' 

656 'C - Set if ACCB bit 7 of result is set; cleared otherwise.' 

657 ), 

658 'description': ( 

659 'Multiply the unsigned binary numbers in the accumulators and place the result in both accumulators (ACCA contains the most-significant byte of the result).\n' 

660 'Unsigned multiply allows multiple-precision operations.' 

661 ), 

662 'instr_desc': 'Unsigned multiply (A * B ? D)', 

663 'mnemonic': {'MUL': {'HNZVC': '--a-a', 

664 'desc': 'D = A*B (Unsigned)'}}, 

665 'operation': "ACCA':ACCB' = ACCA * ACCB", 

666 'source form': 'MUL'}, 

667 'NEG': {'condition code': ( 

668 'H - Undefined.\n' 

669 'N - Set if the result is negative; cleared otherwise.\n' 

670 'Z - Set if the result is zero; cleared otherwise.\n' 

671 'V - Set if the original operand was 10000000 2 .\n' 

672 'C - Set if a borrow is generated; cleared otherwise.' 

673 ), 

674 'description': ( 

675 'Replaces the operand with its twos complement.\n' 

676 'The C (carry) bit represents a borrow and is set to the inverse of the resulting binary carry.\n' 

677 'Note that 80 16 is replaced by itself and only in this case is the V (overflow) bit set.\n' 

678 'The value 00 16 is also replaced by itself, and only in this case is the C (carry) bit cleared.' 

679 ), 

680 'instr_desc': 'Negate accumulator or memory', 

681 'mnemonic': {'NEG': {'HNZVC': 'uaaaa', 

682 'desc': 'M = !M + 1'}, 

683 'NEGA': {'HNZVC': 'uaaaa', 

684 'desc': 'A = !A + 1'}, 

685 'NEGB': {'HNZVC': 'uaaaa', 

686 'desc': 'B = !B + 1'}}, 

687 'operation': "M' = 0 - M", 

688 'source form': 'NEG Q; NEGA; NEG B'}, 

689 'NOP': {'condition code': ( 

690 'This instruction causes only the program counter to be incremented.\n' 

691 'No other registers or memory locations are affected.' 

692 ), 

693 'description': '', 

694 'instr_desc': 'No operation', 

695 'mnemonic': {'NOP': {'HNZVC': '-----', 

696 'desc': 'No Operation'}}, 

697 'operation': 'Not affected.', 

698 'source form': 'NOP'}, 

699 'OR': {'condition code': ( 

700 'H - Not affected.\n' 

701 'N - Set if the result is negative; cleared otherwise.\n' 

702 'Z - Set if the result is zero; cleared otherwise.\n' 

703 'V - Always cleared.\n' 

704 'C - Not affected.' 

705 ), 

706 'description': 'Performs an inclusive OR operation between the contents of accumulator A or B and the contents of memory location M and the result is stored in accumulator A or B.', 

707 'instr_desc': 'OR memory with accumulator', 

708 'mnemonic': {'ORA': {'HNZVC': '-aa0-', 

709 'desc': 'A = A || M'}, 

710 'ORB': {'HNZVC': '-aa0-', 

711 'desc': 'B = B || M'}, 

712 'ORCC': {'HNZVC': 'ddddd', 

713 'desc': 'C = CC || IMM'}}, 

714 'operation': "R' = R OR M", 

715 'source form': 'ORA P; ORB P'}, 

716 'PAGE': {'description': 'Page 1/2 instructions', 

717 'instr_desc': 'Page 2 Instructions prefix', 

718 'mnemonic': {'PAGE 1': {'HNZVC': '+++++', 

719 'desc': 'Page 1 Instructions prefix'}, 

720 'PAGE 2': {'HNZVC': '+++++', 

721 'desc': 'Page 2 Instructions prefix'}}}, 

722 'PSH': {'comment': 'A single register may be placed on the stack with the condition codes set by doing an autodecrement store onto the stack (example: STX ,--S).', 

723 'condition code': 'Not affected.', 

724 'description': 'All, some, or none of the processor registers are pushed onto the hardware stack (with the exception of the hardware stack pointer itself).', 

725 'instr_desc': 'Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack', 

726 'mnemonic': {'PSHS': {'HNZVC': '-----', 

727 'desc': 'S -= 1: MEM(S) = R; Push Register on S Stack'}, 

728 'PSHU': {'HNZVC': '-----', 

729 'desc': 'U -= 1: MEM(U) = R; Push Register on U Stack'}}, 

730 'operation': 'Push Registers on S Stack: S -= 1: MEM(S) = Reg.', 

731 'source form': ( 

732 'b7 b6 b5 b4 b3 b2 b1 b0\n' 

733 'PC U Y X DP B A CC\n' 

734 'push order ->' 

735 )}, 

736 'PUL': {'comment': 'A single register may be pulled from the stack with condition codes set by doing an autoincrement load from the stack (example: LDX ,S++).', 

737 'condition code': 'May be pulled from stack; not affected otherwise.', 

738 'description': 'All, some, or none of the processor registers are pulled from the hardware stack (with the exception of the hardware stack pointer itself).', 

739 'instr_desc': 'Pull A, B, CC, DP, D, X, Y, U, or PC from hardware stack', 

740 'mnemonic': {'PULS': {'HNZVC': 'ccccc', 

741 'desc': 'R=MEM(S) : S += 1; Pull register from S Stack'}, 

742 'PULU': {'HNZVC': 'ccccc', 

743 'desc': 'R=MEM(U) : U += 1; Pull register from U Stack'}}, 

744 'operation': 'Pull Registers from S Stack: Reg. = MEM(S): S += 1', 

745 'source form': ( 

746 'b7 b6 b5 b4 b3 b2 b1 b0\n' 

747 'PC U Y X DP B A CC\n' 

748 '= pull order' 

749 )}, 

750 'RESET': {'description': 'Build the ASSIST09 vector table and setup monitor defaults, then invoke the monitor startup routine.', 

751 'instr_desc': '', 

752 'mnemonic': {'RESET': {'HNZVC': '*****', 

753 'desc': 'Undocumented opcode'}}}, 

754 'ROL': {'condition code': ( 

755 'H - Not affected.\n' 

756 'N - Set if the result is negative; cleared otherwise.\n' 

757 'Z - Set if the result is zero; cleared otherwise.\n' 

758 'V - Loaded with the result of the exclusive OR of bits six and seven of the original operand.\n' 

759 'C - Loaded with bit seven of the original operand.' 

760 ), 

761 'description': ( 

762 'Rotates all bits of the operand one place left through the C (carry) bit.\n' 

763 'This is a 9-bit rotation.' 

764 ), 

765 'instr_desc': 'Rotate accumulator or memory left', 

766 'mnemonic': {'ROL': {'HNZVC': '-aaas', 

767 'desc': 'M = Rotate M left thru carry'}, 

768 'ROLA': {'HNZVC': '-aaas', 

769 'desc': 'A = Rotate A left thru carry'}, 

770 'ROLB': {'HNZVC': '-aaas', 

771 'desc': 'B = Rotate B left thru carry'}}, 

772 'operation': ( 

773 'C = = C\n' 

774 'b7 = b0' 

775 ), 

776 'source form': 'ROL Q; ROLA; ROLB'}, 

777 'ROR': {'condition code': ( 

778 'H - Not affected.\n' 

779 'N - Set if the result is negative; cleared otherwise.\n' 

780 'Z - Set if the result is zero; cleared otherwise.\n' 

781 'V - Not affected.\n' 

782 'C - Loaded with bit zero of the previous operand.' 

783 ), 

784 'description': ( 

785 'Rotates all bits of the operand one place right through the C (carry) bit.\n' 

786 'This is a 9-bit rotation.' 

787 ), 

788 'instr_desc': 'Rotate accumulator or memory right', 

789 'mnemonic': {'ROR': {'HNZVC': '-aa-s', 

790 'desc': 'M = Rotate M Right thru carry'}, 

791 'RORA': {'HNZVC': '-aa-s', 

792 'desc': 'A = Rotate A Right thru carry'}, 

793 'RORB': {'HNZVC': '-aa-s', 

794 'desc': 'B = Rotate B Right thru carry'}}, 

795 'operation': ( 

796 'C -> -> C\n' 

797 'b7 -> b0' 

798 ), 

799 'source form': 'ROR Q; RORA; RORB'}, 

800 'RTI': {'condition code': 'Recovered from the stack.', 

801 'description': ( 

802 'The saved machine state is recovered from the hardware stack and control is returned to the interrupted program.\n' 

803 'If the recovered E (entire) bit is clear, it indicates that only a subset of the machine state was saved (return address and condition codes) and only that subset is recovered.' 

804 ), 

805 'instr_desc': 'Return from interrupt', 

806 'mnemonic': {'RTI': {'HNZVC': '-----', 

807 'desc': 'Return from Interrupt'}}, 

808 'operation': ( 

809 "IFF CCR bit E is set, then: ACCA' ACCB' DPR' IXH' IXL' IYH' IYL' USH' USL' PCH' PCL' = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1 = (SP), SP' = SP+1\n" 

810 "IFF CCR bit E is clear, then: PCH' PCL' = (SP), SP' = SP+1 = (SP), SP' = SP+1" 

811 ), 

812 'source form': 'RTI'}, 

813 'RTS': {'condition code': 'Not affected.', 

814 'description': ( 

815 'Program control is returned from the subroutine to the calling program.\n' 

816 'The return address is pulled from the stack.' 

817 ), 

818 'instr_desc': 'Return from subroutine', 

819 'mnemonic': {'RTS': {'HNZVC': '-----', 

820 'desc': 'Return from subroutine'}}, 

821 'operation': "PCH' = (SP), SP' = SP+1 PCL' = (SP), SP' = SP+1", 

822 'source form': 'RTS'}, 

823 'SBC': {'condition code': ( 

824 'H - Undefined.\n' 

825 'N - Set if the result is negative; cleared otherwise.\n' 

826 'Z - Set if the result is zero; cleared otherwise.\n' 

827 'V - Set if an overflow is generated; cleared otherwise.\n' 

828 'C - Set if a borrow is generated; cleared otherwise.' 

829 ), 

830 'description': ( 

831 'Subtracts the contents of memory location M and the borrow (in the C (carry) bit) from the contents of the designated 8-bit register, and places the result in that register.\n' 

832 'The C bit represents a borrow and is set to the inverse of the resulting binary carry.' 

833 ), 

834 'instr_desc': 'Subtract memory from accumulator with borrow', 

835 'mnemonic': {'SBCA': {'HNZVC': 'uaaaa', 

836 'desc': 'A = A - M - C'}, 

837 'SBCB': {'HNZVC': 'uaaaa', 

838 'desc': 'B = B - M - C'}}, 

839 'operation': "R' = R - M - C", 

840 'source form': 'SBCA P; SBCB P'}, 

841 'SEX': {'condition code': ( 

842 'H - Not affected.\n' 

843 'N - Set if the result is negative; cleared otherwise.\n' 

844 'Z - Set if the result is zero; cleared otherwise.\n' 

845 'V - Not affected.\n' 

846 'C - Not affected.' 

847 ), 

848 'description': 'This instruction transforms a twos complement 8-bit value in accumulator B into a twos complement 16-bit value in the D accumulator.', 

849 'instr_desc': 'Sign Extend B accumulator into A accumulator', 

850 'mnemonic': {'SEX': {'HNZVC': '-aa0-', 

851 'desc': 'Sign extend B into A'}}, 

852 'operation': "If bit seven of ACCB is set then ACCA' = FF 16 else ACCA' = 00 16", 

853 'source form': 'SEX'}, 

854 'ST': {'condition code': ( 

855 'H - Not affected.\n' 

856 'N - Set if the result is negative; cleared otherwise.\n' 

857 'Z - Set if the result is zero; cleared otherwise.\n' 

858 'V - Always cleared.\n' 

859 'C - Not affected.' 

860 ), 

861 'description': 'Writes the contents of an 8-bit register into a memory location.', 

862 'instr_desc': 'Store accumulator to memroy', 

863 'mnemonic': {'STA': {'HNZVC': '-aa0-', 

864 'desc': 'M = A'}, 

865 'STB': {'HNZVC': '-aa0-', 

866 'desc': 'M = B'}, 

867 'STD': {'HNZVC': '-aa0-', 

868 'desc': 'M:M+1 = D'}, 

869 'STS': {'HNZVC': '-aa0-', 

870 'desc': 'M:M+1 = S'}, 

871 'STU': {'HNZVC': '-aa0-', 

872 'desc': 'M:M+1 = U'}, 

873 'STX': {'HNZVC': '-aa0-', 

874 'desc': 'M:M+1 = X'}, 

875 'STY': {'HNZVC': '-aa0-', 

876 'desc': 'M:M+1 = Y'}}, 

877 'operation': "M' = R", 

878 'source form': 'STA P; STB P'}, 

879 'SUB': {'condition code': ( 

880 'H - Undefined.\n' 

881 'N - Set if the result is negative; cleared otherwise.\n' 

882 'Z - Set if the result is zero; cleared otherwise.\n' 

883 'V - Set if the overflow is generated; cleared otherwise.\n' 

884 'C - Set if a borrow is generated; cleared otherwise.' 

885 ), 

886 'description': ( 

887 'Subtracts the value in memory location M from the contents of a designated 8-bit register.\n' 

888 'The C (carry) bit represents a borrow and is set to the inverse of the resulting binary carry.' 

889 ), 

890 'instr_desc': 'Subtract memory from accumulator', 

891 'mnemonic': {'SUBA': {'HNZVC': 'uaaaa', 

892 'desc': 'A = A - M'}, 

893 'SUBB': {'HNZVC': 'uaaaa', 

894 'desc': 'B = B - M'}, 

895 'SUBD': {'HNZVC': '-aaaa', 

896 'desc': 'D = D - M:M+1'}}, 

897 'operation': "R' = R - M", 

898 'source form': 'SUBA P; SUBB P'}, 

899 'SWI': {'condition code': 'Not affected.', 

900 'description': ( 

901 'All of the processor registers are pushed onto the hardware stack (with the exception of the hardware stack pointer itself), and control is transferred through the software interrupt vector.\n' 

902 'Both the normal and fast interrupts are masked (disabled).' 

903 ), 

904 'instr_desc': 'Software interrupt (absolute indirect)', 

905 'mnemonic': {'SWI': {'HNZVC': '-----', 

906 'desc': 'Software interrupt 1'}, 

907 'SWI2': {'HNZVC': '-----',