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MNT Designer
From a few lines of logic to a layout you can explore, refine, and verify.
Synthesize
Refine
Verify
01 / Logic
.v
Verilog
02 / Physical design
Layout canvas
No layout
0 occupied tiles
Your next circuit starts here.
Create a blank layout to place gates, or try the Verilog example and synthesize your first design.
Ready when you are. Import Verilog, try an example, or create a blank layout.