Metadata-Version: 2.4
Name: peakrdl-busdecoder
Version: 0.8.0
Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
Author: Arnav Sacheti
License: LGPLv3
Project-URL: Source, https://github.com/arnavsacheti/PeakRDL-BusDecoder
Project-URL: Tracker, https://github.com/arnavsacheti/PeakRDL-BusDecoder/issues
Project-URL: Changelog, https://github.com/arnavsacheti/PeakRDL-BusDecoder/releases
Project-URL: Documentation, https://arnavsacheti.github.io/PeakRDL-BusDecoder/
Keywords: SystemRDL,PeakRDL,bus decoder,address decoder,hierarchical addressing,compiler,tool,registers,generator,Verilog,SystemVerilog,register abstraction layer,FPGA,ASIC
Classifier: Development Status :: 5 - Production/Stable
Classifier: Programming Language :: Python
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Classifier: Programming Language :: Python :: 3.13
Classifier: Programming Language :: Python :: 3.14
Classifier: Intended Audience :: Developers
Classifier: License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)
Classifier: Operating System :: OS Independent
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Requires-Python: >=3.11
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: jinja2~=3.1
Requires-Dist: systemrdl-compiler~=1.30
Provides-Extra: cli
Requires-Dist: peakrdl-cli>=1.2.3; extra == "cli"
Dynamic: license-file

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# PeakRDL-BusDecoder
Generate a SystemVerilog bus decoder from SystemRDL that splits CPU interface signals to multiple sub-address spaces. This tool is designed for creating hierarchical register address maps by decoding bus transactions and routing them to the appropriate child address maps.

## 0.8.0

Version 0.8.0 requires **Python 3.11 or newer**.

- APB3 and APB4 remain supported in interface and flat-port forms. With default
  `--apb-buffer none`, omitting `--clk-src` preserves the 0.7.x clockless decoder
  ports (`off`). Optional transaction-aware buffering (`in`/`out`/`both`)
  automatically selects `design` clock/reset when unspecified and retires each
  child transfer exactly once. No-wait upstream ACCESS takes 1/2/2/3 cycles for
  `none`/`in`/`out`/`both`. Buffered reset aborts pending work and requires a fresh
  upstream SETUP. See [APB timing and reset behavior](docs/cpuif/apb.rst).
- Ordered **AXI4-Lite** accepts AW and W independently, with separate bounded
  read/write queues, FIFO responses, backpressure, and reset recovery. It now
  requires clock/reset wiring: the default is `design`; `cpuif` is also
  supported, while `off` is rejected.
- Single-manager **AHB-Lite** provides retained address/data-phase routing and
  two-cycle local ERROR responses in interface and flat-port forms. Decoded
  apertures must be at least 1 KiB and aligned/sized in 1 KiB units.
- Project-wide generator defaults in `[busdecoder]` in `peakrdl.toml`, with
  explicit CLI overrides and `--no-gate-signals`/`--no-unroll`/`--no-parametrize`
  to disable project-enabled options. Existing custom CPU-interface aliases
  remain supported. See [configuration](docs/configuring.rst).

This is not full AXI4: IDs, bursts, exclusives, and cross-ID reordering are not
implemented. Read and write routing share one SystemRDL layout; standalone
custom read/write layouts are not implemented.

See [Migrating from 0.7.x](docs/migrating.rst) for Python import updates,
clock/reset choices, and changed decode-depth and AXI4-Lite behavior.

For the command line tool, see the [PeakRDL project](https://peakrdl.readthedocs.io).

## Documentation
See the [PeakRDL-BusDecoder Documentation](https://arnavsacheti.github.io/PeakRDL-BusDecoder/) for more details
