example Project Status (08/01/2017 - 17:05:48)
Project File:	example.xise	Parser Errors:	No Errors
Module Name:	example	Implementation State:	Programming File Generated
Target Device:	xc3s1000-4fg320	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	78 Warnings (48 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	33	15,360	1%
Number of 4 input LUTs	110	15,360	1%
Number of occupied Slices	67	7,680	1%
Number of Slices containing only related logic	67	67	100%
Number of Slices containing unrelated logic	0	67	0%
Total Number of 4 input LUTs	113	15,360	1%
Number used as logic	110
Number used as a route-thru	3
Number of bonded IOBs	62	221	28%
Number of BUFGMUXs	1	8	12%
Average Fanout of Non-Clock Nets	2.16

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Aug 1 17:05:35 2017	0	13 Warnings (13 new)	3 Infos (3 new)
Translation Report	Current	Tue Aug 1 17:05:39 2017	0	20 Warnings (10 new)	0
Map Report	Current	Tue Aug 1 17:05:43 2017	0	0	4 Infos (4 new)
Place and Route Report	Current	Tue Aug 1 17:05:49 2017	0	25 Warnings (15 new)	0
Power Report
Post-PAR Static Timing Report	Current	Tue Aug 1 17:05:52 2017	0	20 Warnings (10 new)	5 Infos (5 new)
Bitgen Report	Current	Tue Aug 1 17:05:56 2017	0	0	1 Info (1 new)

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Log File	Current	Tue Aug 1 17:05:56 2017

Date Generated: 08/01/2017 - 17:05:48