# API

There are 2 interfaces:
  - pysimavr.swig.*: low level, generated by swig
  - pysimavr.*: high level classes, they can redirect function calls to low level interface. Example: Avr class (high level) has all properties and methods of avr_t class (low level) automatically.

## low level interface

class `pysimavr.swig.ac_input.``ac_input_t`
  `avr`
  `irq`
  `value`

class `pysimavr.swig.hd44780.``hd44780_t`
  `avr`
  `cursor`
  `datapins`
  `flags`
  `h`
  `irq`
  `pinstate`
  `readpins`
  `vram`
  `w`

class `pysimavr.swig.inverter.``inverter_t`
  `avr`
  `irq`
  `out`

class `pysimavr.swig.ledrow.``ledrow_t`
  `avr`
  `irq`
  `pinstate`
  `pinstate_changed`

class `pysimavr.swig.sgm7.``sgm7_t`
  `avr`
  `digit_count`
  `digit_pin`
  `digit_port`
  `digit_segments`
  `digit_segments_changed`
  `irq`
  `pinstate`
  `segment_pin`
  `segment_port`

class `pysimavr.swig.simavr.``avr_io_t`
  `avr`
  `dealloc`
  `ioctl`
  `irq`
  `irq_count`
  `irq_ioctl_get`
  `irq_names`
  `kind`
  `next`
  `reset`

class `pysimavr.swig.simavr.``avr_iopin_t`
  `pin`
  `port`

class `pysimavr.swig.simavr.``avr_ioport_external_t`
  `mask`
  `name`
  `value`

class `pysimavr.swig.simavr.``avr_ioport_getirq_t`
  `bit`
  `irq`

class `pysimavr.swig.simavr.``avr_ioport_state_t`
  `ddr`
  `name`
  `pin`
  `port`

class `pysimavr.swig.simavr.``avr_ioport_t`
  `external`
  `io`
  `name`
  `pcint`
  `r_ddr`
  `r_pcint`
  `r_pin`
  `r_port`

class `pysimavr.swig.simavr.``avr_ioport_t_external`
  `pull_mask`
  `pull_value`

class `pysimavr.swig.simavr.``avr_irq_pool_t`
  `count`
  `irq`

class `pysimavr.swig.simavr.``avr_irq_t`
  `flags`
  `hook`
  `irq`
  `name`
  `pool`
  `value`

class `pysimavr.swig.simavr.``avr_kind_t`
  `make`
  `names`

class `pysimavr.swig.simavr.``avr_regbit_t`
  `bit`
  `mask`
  `reg`

class `pysimavr.swig.simavr.``avr_symbol_t`
  `addr`
  `symbol`

class `pysimavr.swig.simavr.``avr_t`
  `address_size`
  `aref`
  `avcc`
  `codeend`
  `custom`
  `cycle`
  `cycle_timers`
  `data`
  `e2end`
  `eind`
  `flash`
  `flashend`
  `frequency`
  `fuse`
  `gdb`
  `gdb_port`
  `init`
  `interrupt_state`
  `interrupts`
  `io`
  `io_port`
  `io_shared_io`
  `io_shared_io_count`
  `irq_pool`
  `log`
  `mmcu`
  `pc`
  `ramend`
  `rampz`
  `reset`
  `reset_pc`
  `run`
  `run_cycle_count`
  `run_cycle_limit`
  `signature`
  `sleep`
  `sleep_usec`
  `sreg`
  `state`
  `trace`
  `trace_data`
  `vcc`
  `vcd`
  `vector_size`

class `pysimavr.swig.simavr.``avr_t_custom`
  `data`
  `deinit`
  `init`

class `pysimavr.swig.simavr.``avr_t_io`
  `irq`
  `r`
  `w`

class `pysimavr.swig.simavr.``avr_t_io_r`
  `c`
  `param`

class `pysimavr.swig.simavr.``avr_t_io_shared_io`
  `io`
  `used`

class `pysimavr.swig.simavr.``avr_t_io_shared_io_io`
  `c`
  `param`

class `pysimavr.swig.simavr.``avr_t_io_w`
  `c`
  `param`

class `pysimavr.swig.simavr.``avr_trace_data_t`
  `codeline`
  `old`
  `old_pci`
  `touched`

class `pysimavr.swig.simavr.``avr_trace_data_t_old`
  `pc`
  `sp`

class `pysimavr.swig.simavr.``avr_vcd_log_t`
  `signal`
  `value`
  `when`

class `pysimavr.swig.simavr.``avr_vcd_signal_t`
  `alias`
  `irq`
  `name`
  `size`

class `pysimavr.swig.simavr.``avr_vcd_t`
  `avr`
  `filename`
  `log`
  `logindex`
  `logsize`
  `output`
  `period`
  `signal`
  `signal_count`
  `start`

class `pysimavr.swig.simavr.``elf_firmware_t`
  `aref`
  `avcc`
  `bsssize`
  `command_register_addr`
  `console_register_addr`
  `datasize`
  `eeprom`
  `eesize`
  `external_state`
  `flash`
  `flashbase`
  `flashsize`
  `frequency`
  `mmcu`
  `symbol`
  `symbolcount`
  `trace`
  `tracecount`
  `tracename`
  `traceperiod`
  `vcc`

class `pysimavr.swig.simavr.``elf_firmware_t_external_state`
  `mask`
  `port`
  `value`

class `pysimavr.swig.simavr.``elf_firmware_t_trace`
  `addr`
  `mask`
  `name`

## high level interface

class `pysimavr.ac.``Ac`(avr)
  `getirq`(pin)

`pysimavr.connect.``connect_irqs`(irq_out, irq_in, bidirectional=False)

`pysimavr.connect.``connect_pins_by_rule`(rule, device_map, vcd=None)

  rule example:

  B0 –> D4 -> vcd

  B1 <== D5 B2 => D6 # B3 <=> D7

class `pysimavr.firmware.``Firmware`(filename=None)
  `mcu`
  `read`(filename)

class `pysimavr.inverter.``Inverter`(avr)
  `getirq`(pin)
  `out`(i)

class `pysimavr.lcd.``Lcd`(avr, size=(20, 2))
  `get_char`(x, y)
  `getirq`(pin)
  `pinstate`(pin)
  `reset`()

class `pysimavr.ledrow.``LedRow`(avr, size=8)
  `getirq`(pin)
  `pinstate`(i)
  `reset_dirty`(i)

    read and reset

class `pysimavr.sgm7.``Sgm7`(avr, size=4)
  `digit_segments`(digit_index)
  `getirq`(pin)
  `pinindex`(pin_name)
  `pinstate`(pin)
  `reset_dirty`(digit_index)

    read and reset

class `pysimavr.vcdfile.``VcdFile`(avr, filename='gtkwave_output.vcd', period=10)
  `add_signal`(irq, name=None, bits=1)
  `start`()
  `stop`()
  `terminate`()