# pysimavr.swig package

## Submodules

## pysimavr.swig.ac_input module

class `pysimavr.swig.ac_input.``ac_input_t`

  Bases: `object`

  `avr`
  `irq`
  `value`

## pysimavr.swig.button module

## pysimavr.swig.hd44780 module

class `pysimavr.swig.hd44780.``hd44780_t`

  Bases: `object`

  `avr`
  `cursor`
  `datapins`
  `flags`
  `h`
  `irq`
  `pinstate`
  `readpins`
  `vram`
  `w`

## pysimavr.swig.inverter module

class `pysimavr.swig.inverter.``inverter_t`

  Bases: `object`

  `avr`
  `irq`
  `out`

## pysimavr.swig.ledrow module

class `pysimavr.swig.ledrow.``ledrow_t`

  Bases: `object`

  `avr`
  `irq`
  `pinstate`
  `pinstate_changed`

## pysimavr.swig.sgm7 module

class `pysimavr.swig.sgm7.``sgm7_t`

  Bases: `object`

  `avr`
  `digit_count`
  `digit_pin`
  `digit_port`
  `digit_segments`
  `digit_segments_changed`
  `irq`
  `pinstate`
  `segment_pin`
  `segment_port`

## pysimavr.swig.simavr module

class `pysimavr.swig.simavr.``avr_io_t`

  Bases: `object`

  `avr`
  `dealloc`
  `ioctl`
  `irq`
  `irq_count`
  `irq_ioctl_get`
  `irq_names`
  `kind`
  `next`
  `reset`

class `pysimavr.swig.simavr.``avr_iopin_t`

  Bases: `object`

  `pin`
  `port`

class `pysimavr.swig.simavr.``avr_ioport_external_t`

  Bases: `object`

  `mask`
  `name`
  `value`

class `pysimavr.swig.simavr.``avr_ioport_getirq_t`

  Bases: `object`

  `bit`
  `irq`

class `pysimavr.swig.simavr.``avr_ioport_state_t`

  Bases: `object`

  `ddr`
  `name`
  `pin`
  `port`

class `pysimavr.swig.simavr.``avr_ioport_t`

  Bases: `object`

  `external`
  `io`
  `name`
  `pcint`
  `r_ddr`
  `r_pcint`
  `r_pin`
  `r_port`

class `pysimavr.swig.simavr.``avr_ioport_t_external`

  Bases: `object`

  `pull_mask`
  `pull_value`

class `pysimavr.swig.simavr.``avr_irq_pool_t`

  Bases: `object`

  `count`
  `irq`

class `pysimavr.swig.simavr.``avr_irq_t`

  Bases: `object`

  `flags`
  `hook`
  `irq`
  `name`
  `pool`
  `value`

class `pysimavr.swig.simavr.``avr_kind_t`

  Bases: `object`

  `make`
  `names`

class `pysimavr.swig.simavr.``avr_regbit_t`

  Bases: `object`

  `bit`
  `mask`
  `reg`

class `pysimavr.swig.simavr.``avr_symbol_t`

  Bases: `object`

  `addr`
  `symbol`

class `pysimavr.swig.simavr.``avr_t`

  Bases: `object`

  `address_size`
  `aref`
  `avcc`
  `codeend`
  `custom`
  `cycle`
  `cycle_timers`
  `data`
  `e2end`
  `eind`
  `flash`
  `flashend`
  `frequency`
  `fuse`
  `gdb`
  `gdb_port`
  `init`
  `interrupt_state`
  `interrupts`
  `io`
  `io_port`
  `io_shared_io`
  `io_shared_io_count`
  `irq_pool`
  `log`
  `mmcu`
  `pc`
  `ramend`
  `rampz`
  `reset`
  `reset_pc`
  `run`
  `run_cycle_count`
  `run_cycle_limit`
  `signature`
  `sleep`
  `sleep_usec`
  `sreg`
  `state`
  `trace`
  `trace_data`
  `vcc`
  `vcd`
  `vector_size`

class `pysimavr.swig.simavr.``avr_t_custom`

  Bases: `object`

  `data`
  `deinit`
  `init`

class `pysimavr.swig.simavr.``avr_t_io`

  Bases: `object`

  `irq`
  `r`
  `w`

class `pysimavr.swig.simavr.``avr_t_io_r`

  Bases: `object`

  `c`
  `param`

class `pysimavr.swig.simavr.``avr_t_io_shared_io`

  Bases: `object`

  `io`
  `used`

class `pysimavr.swig.simavr.``avr_t_io_shared_io_io`

  Bases: `object`

  `c`
  `param`

class `pysimavr.swig.simavr.``avr_t_io_w`

  Bases: `object`

  `c`
  `param`

class `pysimavr.swig.simavr.``avr_trace_data_t`

  Bases: `object`

  `codeline`
  `old`
  `old_pci`
  `touched`

class `pysimavr.swig.simavr.``avr_trace_data_t_old`

  Bases: `object`

  `pc`
  `sp`

class `pysimavr.swig.simavr.``avr_vcd_log_t`

  Bases: `object`

  `signal`
  `value`
  `when`

class `pysimavr.swig.simavr.``avr_vcd_signal_t`

  Bases: `object`

  `alias`
  `irq`
  `name`
  `size`

class `pysimavr.swig.simavr.``avr_vcd_t`

  Bases: `object`

  `avr`
  `filename`
  `log`
  `logindex`
  `logsize`
  `output`
  `period`
  `signal`
  `signal_count`
  `start`

class `pysimavr.swig.simavr.``elf_firmware_t`

  Bases: `object`

  `aref`
  `avcc`
  `bsssize`
  `command_register_addr`
  `console_register_addr`
  `datasize`
  `eeprom`
  `eesize`
  `external_state`
  `flash`
  `flashbase`
  `flashsize`
  `frequency`
  `mmcu`
  `symbol`
  `symbolcount`
  `trace`
  `tracecount`
  `tracename`
  `traceperiod`
  `vcc`

class `pysimavr.swig.simavr.``elf_firmware_t_external_state`

  Bases: `object`

  `mask`
  `port`
  `value`

class `pysimavr.swig.simavr.``elf_firmware_t_trace`

  Bases: `object`

  `addr`
  `mask`
  `name`

## pysimavr.swig.spk module

## pysimavr.swig.uart_buff module

## pysimavr.swig.uart_udp module

## Module contents