# Test vectors for TransfertControl ports
# 0 means force 0
# 1 means force 1
# L means expect 0
# H means expect 1
# X means don’t care
########################
## Clock cycle = 10ns ##
########################
#time Rst   Clk   FifoIn_IsEmpty   HS_AckTx         FifoIn_DataOut(15:0)
0     1     0     1                0                0000000000000000
5     1     1     1                0                0000000000000000
10    0     0     1                0                0000000000000000 
15    0     1     1                0                0000000000000000 
20    0     0     0                0                0000000000000000 
# Packet arrival on port
25    0     1     1                0                0000000000000001 
30    0     0     1                0                0000000000000001 
35    0     1     0                1                0000000000000001 
40    0     0     0                1                0000000000000001 
45    0     1     1                1                0000000000000010 
50    0     0     1                1                0000000000000010 
55    0     1     0                1                0000000000000010 
60    0     0     0                1                0000000000000010 
65    0     1     1                1                0000000000000010
70    0     0     1                1                0000000000000011
75    0     1     0                1                0000000000000011
80    0     0     0                1                0000000000000011
85    0     1     0                1                0000000000000011
90    0     0     0                1                0000000000000100
95    0     1     0                1                0000000000000100
100   0     0     0                1                0000000000000100
105   0     1     0                0                0000000000000100
# Packet arrival on port 1 and 3
110   0     0     0                0                0000000000000101
115   0     1     0                0                0000000000000101
120   0     0     0                0                0000000000000101
125   0     1     0                0                0000000000000101
130   0     0     0                0                0000000000000101
135   0     1     0                0                0000000000000101
# 3 packets arrival on all ports
140   0     0     0                0                0000000000010101
145   0     1     0                0                0000000000010110
150   0     0     0                0                0000000000010111
155   0     1     0                0                0000000000011000
160   0     0     0                0                0000000000011001
165   0     1     0                0                0000000000011010
170   0     0     0                0                0000000000011011
175   0     1     0                1                0000000000011100
180   0     0     0                1                0000000000011101
185   0     1     0                0                0000000000011110
190   0     0     0                0                0000000000011111
195   0     1     0                0                0000000000100000
200   0     0     0                0                0000000000100001
205   0     1     0                0                0000000000100010
210   0     0     0                0                0000000000100011
215   0     1     0                0                0000000000100100
220   0     0     0                0                0000000000100101
225   1     1     0                0                0000000000100110

230   1     0     0                0                0000000000100111


