<node description="Transactor interface test block" tags="slave">

Block to allow testing of 'out-of-band' interface to transactor. This interface
is currently used by the uTCA MMC and the simulation testbench, but could also (e.g.)
interface to an on-chip CPU or PCIe slave.

	<node id="data" address="0x0"/>
	
Data to be read / written to or from the transactor buffer (16b words).
	
	<node id="cmd" address="0x1">
	
Note that this register is not properly handled across clock domains, so only
ever set one bit at a time (otherwise they will not be synchronised on chip).
	
		<node id="write" address="0x1"/>
		
Set to write a data word to the transactor buffer (edge-sensitive).
		
		<node id="read" address="0x2"/>
		
Set to read a data word from the transactor buffer (edge-sensitive).
		
		<node id="req" address="0x4"/>
		
Set to request processing of packet by the transactor (edge-sensitive).
		
		<node id="done" address="0x8"/>
		
Indicates the 'done' status of the transactor buffer.
		
	</node>
</node>

