Chapter 31. FAQ
| Part V. FAQ |

## Chapter 31. FAQ

This page contains a list of accummulated Frequently Asked Questions. If you are having difficulties using Covered or have questions that are not answered in the User's Guide, please check this list for answers. If you do not find the information that you are looking for in the User's Guide or this FAQ, please send an e-mail to:

`<phase1geo@gmail.com>`

31.1. Is a CDD file generated from a newer version of Covered compatible with a CDD file generated from an older version?
31.2. When I run the score command, Covered seems to take a long time to run. Is there anything that I can do to speed up scoring?
31.3. I get an assertion error when running Covered, what should I do?
31.4. Covered is giving me a parser error for Verilog code that seems to be syntactically correct. What is wrong?
31.5. Is Covered's Verilog parser Verilog-2001 compliant?
31.6. What is the difference between the stable release and the development release?

31.1. | Is a CDD file generated from a newer version of Covered compatible with a CDD file generated from an older version?
| The answer to this question is, "Well, that depends...". Since the format of the CDD file is only used by Covered, the contents and format of this file may be changed to suit the needs of Covered. This means that it is possible for a CDD file created from an older version of Covered to be incompatible with a newer version. Additionally, the developers of Covered will not make any attempts to make sure that older CDD files can be properly read by a newer version of Covered. It is suggested that any CDD files generated from a particular version of Covered be merged and/or reported on by that same version, and if Covered is upgraded, new CDD files should be generated. This being said, it is also a possibility that between versions of Covered a "backwards compatibility" may be maintained if a change to this file's format is not required.
31.2. | When I run the score command, Covered seems to take a long time to run. Is there anything that I can do to speed up scoring?
- | While Covered is continuously being enhanced to provide better performance for all commands (especially the score command), it may still take a while to complete scoring if one or more of the following is true: The design being scored is sufficiently large The VCD/LXT2/FST dumpfile is sufficiently large The VCD/LXT2/FST dumpfile contains dump information for a part of the design not being scored When Covered was configured, the --enable-debug and/or --enable-profiling options were specified If reason (1) is true, speeding up each run can be achieved by one of the following suggestions: Reduce the scored design in size by eliminating modules or constructs from its design tree. (See Section 9.3, “Specifying What to Cover” for more information on how to accomplish this) Split up the design into smaller parts along module boundaries and generate coverage for those parts.
  | Note
  It is not currently possible to append these modules into one file. Merging and reporting must be done on these smaller pieces independently from one another.
If reason (2) is true, nothing can be done except to shorten the run time of the diagnostics to produce shorter dumpfiles. If reason (3) is true, the $dumpvars call in the simulator should be modified to only generate VCD/LXT2/FST dump information for the modules included in scoring. If there are modules not being scored which are included in the $dumpvars calls, please remove these unnecessary modules from dumpfile output. If reason (4) is true, Covered should be reconfigured without these options specified. The debugging and profiling facilities are enormous performance degraders and immediate simulation performance enhancement will be seen if Covered is rebuilt without these options specified. If you believe that you have a situation which is void of these prevailing reasons and Covered is still running slowly, please send an e-mail to me. I will consider these problems to be of lower priority than actual bugs but will look into the situation to see where code can be optimized.
31.3. | I get an assertion error when running Covered, what should I do?
| Covered uses C assertions to make sure that internal pointers are not be referenced when NULL and that certain internal situations do not arise. If you receive some type of assertion error when running Covered, it means that something went wrong internally in Covered. The error is NOT due to user error. Please submit a bug report containing the assertion error message, file and line number. Additionally, run the Covered command with the -D global option (covered -D command) and provide the output from doing this with the bug report (please only specify tail of output if the output is too lengthy). If Covered provides any other type of error message (something other than a core dump), Covered has found a user error that must be fixed by the user. Please do not submit bug reports if these errors are encountered, unless you wish to add a question about it to the FAQ.
31.4. | Covered is giving me a parser error for Verilog code that seems to be syntactically correct. What is wrong?
| If Covered displays a syntax (parse) error during the score command and the Verilog code is written correctly, it is because Covered's parser is incomplete. Please submit a bug or send an e-mail containing a code snippet of the unsupported Verilog.
31.5. | Is Covered's Verilog parser Verilog-2001 compliant?
| This is currently being worked on. The parser should properly parse all code; however, not all Verilog-2001 constructs are considered for coverage due to lack of support for them in Covered's core. If there is code that will not parse that should, please submit a bug report for this.
31.6. | What is the difference between the stable release and the development release?
| Covered's development consists of two active "branches": the stable branch and the development branch. When a new stable branch is created (ex. 0.4 or 0.5), it represents the latest version of the development branch. As Covered's development branch is worked on (adding new features, changes to the core, etc.), the stable branch remains in a feature frozen stage. Only bug fixes, documentation updates or minor enhancements (changes that will not affect the core code) are made to the stable branch. When a number of these changes have been accumulated on the stable branch, a snapshot of the stable branch is made available for public download (ex. 0.4.1). User's of the stable release should expect no major feature changes from minor rev to minor rev and should expect a somewhat polished version of the project (few if any bugs and correct user documentation). User's of the development releases should expect to see more bugs and fewer documentation consistencies (although an attempt is made to minimize both) but should expect lots of feature additions, optimizations, improvements, etc. from release to release. Bug findings found in the stable release are applied to the development branch when applicable. It is important to note that both the stable and development releases contain a regression testbench that must fully pass before either release is made. This should minimize bugs in both releases and give user's of either branch a level of confidence that the release is usable.

Part V. FAQ |  | Part VI. Epilogue