RISC-V Platform-Level Interrupt Controller (PLIC)
-------------------------------------------------

The RISC-V supervisor ISA specification allows for the presence of a
platform-level interrupt controller (PLIC).   The PLIC connects all external
interrupts in the system to all hart contexts in the system, via the external
interrupt source in each hart's hart-local interrupt controller (HLIC).  A hart
context is a privilege mode in a hardware execution thread.  For example, in
an 4 core system with 2-way SMT, you have 8 harts and probably at least two
privilege modes per hart; machine mode and supervisor mode.

Each interrupt can be enabled on per-context basis. Any context can claim
a pending enabled interrupt and then release it once it has been handled.

Each interrupt has a configurable priority. Higher priority interrupts are
serviced firs. Each context can specify a priority threshold. Interrupts
with priority below this threshold will not cause the PLIC to raise its
interrupt line leading to the context.

While the PLIC supports both edge-triggered and level-triggered interrupts,
interrupt handlers are oblivious to this distinction and therefor it is not
specific in the PLIC device-tree binding.

While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
"riscv,plic0" device is a concrete implementation of the PLIC that contains a
specific memory layout.  More details about the memory layout of the
"riscv,plic0" device can be found as a comment in the device driver, or as part
of the SiFive U5 Coreplex Series Manual (page 22 of the PDF of version 1.0)
<https://www.sifive.com/documentation/coreplex/u5-coreplex-series-manual/>

Required properties:
- compatible : "riscv,plic0"
- #address-cells : should be <0>
- #interrupt-cells : should be <1>
- interrupt-controller : Identifies the node as an interrupt controller
- reg : Should contain 1 register range (address and length)
- interrupts-extended : Specifies which contexts are connected to the PLIC,
  with "-1" specifying that a context is not present.

Example:

	plic: interrupt-controller@c000000 {
		#address-cells = <0>;
		#interrupt-cells = <1>;
		compatible = "riscv,plic0";
		interrupt-controller;
		interrupts-extended = <
			&cpu0-intc 11
			&cpu1-intc 11 &cpu1-intc 9
			&cpu2-intc 11 &cpu2-intc 9
			&cpu3-intc 11 &cpu3-intc 9
			&cpu4-intc 11 &cpu4-intc 9>;
		reg = <0xc000000 0x4000000>;
		riscv,ndev = <10>;
	};
