clash-lib-0.99.2: CAES Language for Synchronous Hardware - As a Library

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

• Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
• Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
• Higher-order functions, with type inference, result in designs that are fully parametric by default.
• Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.
• Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

• The CoreHW internal language: SystemF + Letrec + Case-decomposition
• The normalisation process that brings CoreHW in a normal form that can be converted to a netlist
• Blackbox/Primitive Handling

Front-ends (for: parsing, typecheck, etc.) are provided by separate packages:

• GHC/Haskell Frontend
• Idris Frontend

Prelude library: http://hackage.haskell.org/package/clash-prelude