clash-lib-0.99.2: CAES Language for Synchronous Hardware - As a Library

Copyright	(C) 2015-2016 University of Twente 2017 Google Inc.
License	BSD2 (see the file LICENSE)
Maintainer	Christiaan Baaij <christiaan.baaij@gmail.com>
Safe Haskell	None
Language	Haskell2010

Clash.Backend.Verilog

Description

Generate Verilog for assorted Netlist datatypes

Synopsis

data VerilogState
include :: Monad m => [Text] -> Mon m Doc

Documentation

data VerilogState #

State for the VerilogM monad:

Instances

Backend VerilogState #

Instance details

Defined in Clash.Backend.Verilog

Methods

initBackend :: Int -> HdlSyn -> VerilogState #

hdlKind :: VerilogState -> HDL #

primDirs :: VerilogState -> IO [FilePath] #

name :: VerilogState -> String #

extension :: VerilogState -> String #

extractTypes :: VerilogState -> HashSet HWType #

genHDL :: String -> SrcSpan -> Component -> Mon (State VerilogState) ((String, Doc), [(String, Doc)]) #

mkTyPackage :: String -> [HWType] -> Mon (State VerilogState) [(String, Doc)] #

hdlType :: Usage -> HWType -> Mon (State VerilogState) Doc #

hdlTypeErrValue :: HWType -> Mon (State VerilogState) Doc #

hdlTypeMark :: HWType -> Mon (State VerilogState) Doc #

hdlRecSel :: HWType -> Int -> Mon (State VerilogState) Doc #

hdlSig :: Text -> HWType -> Mon (State VerilogState) Doc #

genStmt :: Bool -> State VerilogState Doc #

inst :: Declaration -> Mon (State VerilogState) (Maybe Doc) #

expr :: Bool -> Expr -> Mon (State VerilogState) Doc #

iwWidth :: State VerilogState Int #

toBV :: HWType -> Text -> Mon (State VerilogState) Doc #

fromBV :: HWType -> Text -> Mon (State VerilogState) Doc #

hdlSyn :: State VerilogState HdlSyn #

mkIdentifier :: State VerilogState (IdType -> Identifier -> Identifier) #

extendIdentifier :: State VerilogState (IdType -> Identifier -> Identifier -> Identifier) #

setModName :: ModName -> VerilogState -> VerilogState #

setSrcSpan :: SrcSpan -> State VerilogState () #

getSrcSpan :: State VerilogState SrcSpan #

blockDecl :: Text -> [Declaration] -> Mon (State VerilogState) Doc #

unextend :: State VerilogState (Identifier -> Identifier) #

addInclude :: (String, Doc) -> State VerilogState () #

addLibraries :: [Text] -> State VerilogState () #

addImports :: [Text] -> State VerilogState () #

include :: Monad m => [Text] -> Mon m Doc #