-- Hoogle documentation, generated by Haddock
-- See Hoogle, http://www.haskell.org/hoogle/


-- | CAES Language for Synchronous Hardware
--   
--   CλaSH (pronounced ‘clash’) is a functional hardware description
--   language that borrows both its syntax and semantics from the
--   functional programming language Haskell. The CλaSH compiler transforms
--   these high-level descriptions to low-level synthesizable VHDL,
--   Verilog, or SystemVerilog.
--   
--   Features of CλaSH:
--   
--   <ul>
--   <li>Strongly typed, but with a very high degree of type inference,
--   enabling both safe and fast prototyping using concise
--   descriptions.</li>
--   <li>Interactive REPL: load your designs in an interpreter and easily
--   test all your component without needing to setup a test bench.</li>
--   <li>Higher-order functions, with type inference, result in designs
--   that are fully parametric by default.</li>
--   <li>Synchronous sequential circuit design based on streams of values,
--   called <tt>Signal</tt>s, lead to natural descriptions of feedback
--   loops.</li>
--   <li>Support for multiple clock domains, with type safe clock domain
--   crossing.</li>
--   </ul>
--   
--   This package provides:
--   
--   <ul>
--   <li>CλaSH Compiler binary using GHC/Haskell as a frontend</li>
--   </ul>
--   
--   Prelude library:
--   <a>http://hackage.haskell.org/package/clash-prelude</a>
@package clash-ghc
@version 0.99.2

module Clash.Main
defaultMain :: [String] -> IO ()
