\documentclass{ppex}
\nonstopmode
\usepackage {timing}
\pagestyle{empty}

\begin{document}
\ResetPreambleCommands
\ReadyForTheFray
\usepackage {timing}
\begin{timing}[2s]{1.4cm}
\tnote{0.5}{4}{$\mathrm{T}_1$}
\tnote{0.5}{12}{$\mathrm{T}_2$}\tnote{0.5}{20}{$\mathrm{T}_i$}
\tnote{0.5}{28}{$\mathrm{T}_1$}\tnote{0.5}{36}{$\mathrm{T}_2$}
\tnote{0.5}{44}{$\mathrm{T}_i$}\tnote{0.5}{52}{$\mathrm{T}_1$}
%% Clock               ....1111....2222....iiii....1111....2222....iiii....1111
\tin{1}{CLK}   \til{1}{HHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLLHHHHLLLL}
%% Adresses line       ....1111....2222....iiii....1111....2222....iiii....1111
\tin{2}{ADDR}  \til{2}{VVVVXVVVVVVVVVVVVVVVXVVVVVVVXVVVVVVVVVVVVVVVXVVVVVVXVVVV}
\tnote{1.85}{10}{Valid}\tnote{1.85}{22}{Invalid}%
\tnote{1.85}{34}{Valid}\tnote{1.85}{46}{Invalid}
%% Adresses status     ....1111....2222....iiii....1111....2222....iiii....1111
\tin{3}{ADS\#} \til{3}{HHHHLLLLLLLLHHHHHHHHHHHHHHHHLLLLLLLLHHHHHHHHHHHHHHHHLLLL}
%% Write/Read          ....1111....2222....iiii....1111....2222....iiii....1111
\tin{4}{W/R\#} \til{4}{HHHHLLLLLLLLLLLLLLLLFFFFFFFFHHHHHHHHHHHHHHHHFFFFFFFFLLLL}
%% Burst ready         ....1111....2222....iiii....1111....2222....iiii....1111
\tin{5}{BRDY\#}\til{5}{UUUUUUUUUUUUZZZZZZZZUUUUUUUUUUUUUUUUZZZZZZZZUUUUUUUUUUUU}
%% Data lines          ....1111....2222....iiii....1111....2222....iiii....1111
\tin{6}{DATA}  \til{6}{ZZZZZZZZZZZZVVVVVVVVZZZZZZZZZZZZZZZZVVVVVVVVZZZZZZZZZZZZ}
\tnote{5.85}{14}{To CPU}\tnote{5.85}{37}{From CPU}
\sline{0.6}{0}{6.}\sline{0.6}{8}{6.}\sline{0.3}{16}{5.5}\sline{0.6}{24}{1.5}
\sline{2.1}{24}{6.}\sline{0.6}{32}{6.}\sline{0.3}{40}{5.5}\sline{0.6}{48}{1.5}
\sline{2.1}{48}{6.}\sline{0.6}{56}{6.}
\end{timing}
\end{document}
